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The block provides five filter coefficients. The direct form systolic architecture provides a fully parallel implementation that makes efficient use of Intel® and Xilinx® DSP blocks. The direct form transposed architecture is a fully parallel implementation and is suitable for FPGA and ASIC applications. The partly serial systolic architecture provides a configurable serial implementation that makes efficient use of FPGA DSP blocks. For a filter implementation that matches multipliers, pipeline registers, and pre-adders to the DSP configuration of your FPGA vendor, specify your target device when you generate HDL code.

You can use the direct-form and transposed-form systolic FIR filter implementations by using the bit-sequencing process or the conventional window-by-window approach. If you use the bit-sequencing process, each filter coefficient is loaded into the filter as a series of bits, starting at the LSB of the coefficient. However, if you use the conventional window-by-window approach, each filter coefficient is loaded into the filter as a series of bits, starting at the MSB of the coefficient.

The bit-sequencing process is generally used to handle sequences of coefficients that are loaded sequentially as a series of bits. The bit-sequencing process uses a bit-by-bit ripple carry technique to load and store bit data from and to the filter. This technique is an efficient way to handle full-word (16-bit) loads.

The conventional window-by-window approach is generally used to handle sequences of coefficients that are loaded concurrently. The window-by-window method is inefficient for full-word (16-bit) loads because it requires the multiplier to operate at the frequency of the source data. For example, suppose you use the window-by-window approach to load four 16-bit coefficients into a 32-bit multiplier. The two middle bits can be loaded at the same time, but the top and bottom bits can only be loaded one at a time. d2c66b5586